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一次v240串口错误(主频错误)  

2009-01-14 11:07:07|  分类: unix |  标签: |举报 |字号 订阅

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高工那的他新的主板和两块新的cpu 及四根内存条,其中cpu0、cpu1处各两个,在串口的输出信息如下:

ALOM - POST run incomplete previously, no POST this time

ALOM BOOTMON v1.3.0
ALOM Build Release: 007
Reset register: e0000000 EHRS ESRS LLRS

Check for Handshake

Returned from Boot Monitor and Handshake

Clearing Memory Cells
Memory Clean Complete

Loading the runtime image...
SC Alert: SC System booted.

SC Alert: Host System has Reset


Sun(tm) Advanced Lights Out Manager 1.3 (V250)

VxDiag not performed.


Enter #. to return to ALOM.
0>Init CPU

0>DMMU

0>DMMU TLB DATA RAM Access

0>DMMU TLB TAGS Access

0>IMMU Registers Access

0>IMMU TLB DATA RAM Access

0>IMMU TLB TAGS Access

0>Init mmu regs

0>Setup L2 Cache

0>L2 Cache Control = 00000000.00f04400

0> Size = 00000000.00100000...

0>Scrub and Setup L2 Cache

0>Setup and Enable DMMU

0>Setup DMMU Miss Handler

0>Test and Init Temp Mailbox

0>CPU Tick and Tick Compare Registers Test

0>CPU Stick and Stick Compare Registers Test

0>Set Timing

0> UltraSPARC[TM] IIIi, Version 2.4

1>L2 Cache Tags Test

1>Init CPU

1> UltraSPARC[TM] IIIi, Version 2.4

1>DMMU

1>DMMU TLB DATA RAM Access

1>DMMU TLB TAGS Access

1>IMMU Registers Access

1>IMMU TLB DATA RAM Access

1>IMMU TLB TAGS Access

1>Init mmu regs

1>Setup L2 Cache

1>L2 Cache Control = 00000000.00f04400

1> Size = 00000000.00100000...

1>Scrub and Setup L2 Cache

1>Setup and Enable DMMU

1>Setup DMMU Miss Handler

1>Test and Init Temp Mailbox

1>CPU Tick and Tick Compare Registers Test

1>CPU Stick and Stick Compare Registers Test

1>Setup Int Handlers

0>Setup Int Handlers

0>Send Int CPU 1

1>Send Int to Master CPU

0>Initialize I2C Controller

0>MB: Part-Dash-Rev#:  3753150-04-0G Serial#:  089944

0>CPU0 MB/P0/B0/D0:

0>Part#:  36VDDT12872G-26AC0  Serial#:  072ac35b  Date Code:  0425  Rev#:  0000

0>CPU0 MB/P0/B0/D1:

0>Part#:  36VDDT12872G-26AC0  Serial#:  072ac37e  Date Code:  0425  Rev#:  0000

0>CPU1 MB/P1/B0/D0:

0>Part#:  36VDDT12872G-26AC0  Serial#:  072ac3bc  Date Code:  0425  Rev#:  0000

0>CPU1 MB/P1/B0/D1:

0>Part#:  36VDDT12872G-26AC0  Serial#:  072ac381  Date Code:  0425  Rev#:  0000

0>Set CPU/System Speed

0>Jumper data = 3c

0>..

0>Send MC Timing CPU 1

0>Probe Dimms

1>Probe Dimms

1>Init Mem Controller Regs

0>Init Mem Controller Regs

1>Set JBUS config reg

0>Set JBUS config reg

0>IO-Bridge unit 0 init test            

0>IO-Bridge unit 1 init test            

0>Do PLL reset

0>Setting timing to 8:1 10:1, system frequency 160 MHz, CPU frequency 1280 MHz

0>Soft Power-on RST thru SW

0>CPUs present in system: 0 1

0>

0>Resume selftest...

0>Init SB

0>Init CPU

0>Init mmu regs

0>Setup L2 Cache

0>L2 Cache Control = 00000000.00f04400

0> Size = 00000000.00100000...

0>Setup and Enable DMMU

0>Setup DMMU Miss Handler

0>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.

0> UltraSPARC[TM] IIIi, Version 2.4

1>Init CPU

1> UltraSPARC[TM] IIIi, Version 2.4

1>Init mmu regs

1>Setup L2 Cache

1>L2 Cache Control = 00000000.00f04400

1> Size = 00000000.00100000...

1>Setup and Enable DMMU

1>Setup DMMU Miss Handler

1>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.

0>Initialize I2C Controller

1>Init Mem Controller Sequence

0>Init Mem Controller Sequence

0>IO-Bridge unit 0 init test            

0>IO-Bridge unit 1 init test            

0>Select Bank Config

0>Probe and Setup Memory

0>INFO: 1024MB Bank 0, Dimm Type X4

0>INFO: 1024MB Bank 1, Dimm Type X4

0>INFO: No memory detected in Bank 2

0>INFO: No memory detected in Bank 3

0>

0>Data Bitwalk on Master

0> Test Bank 0.

0> Test Bank 1.

0>Address Bitwalk on Master

0>INFO: Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to 00000000.40000000.

0>INFO: Addr walk mem test on CPU 0 Bank 1: 00000001.00000000 to 00000001.40000000.

0>Set Mailbox

0>Final mc1 is 50000006.3e581c4e.

0>Setup Final DMMU Entries

0>Post Image Region Scrub

0>Run POST from Memory

0>Verifying checksum on copied image.

0>The Memory's CHECKSUM value is 1e09.

0>The Memory's Content Size value is 5c60.

0>Success...  Checksum on Memory Validated.

1>Select Bank Config

1>Probe and Setup Memory

1>INFO: 1024MB Bank 0, Dimm Type X4

1>INFO: 1024MB Bank 1, Dimm Type X4

1>INFO: No memory detected in Bank 2

1>INFO: No memory detected in Bank 3

1>

1>Set Mailbox

1>Final mc1 is 50000006.3e581c4e.

0>Data Bitwalk on Slave 1

0> Test Bank 0.

0> Test Bank 1.

0>Address Bitwalk on Slave 1

0>INFO: Addr walk mem test on CPU 1 Bank 0: 00000010.00000000 to 00000010.40000000.

0>INFO: Addr walk mem test on CPU 1 Bank 1: 0000
SC Alert: TEMP_SENSOR @ MB.P0.T_CORE has exceeded high warning threshold.
0011.00000000 to 00000011.40000000.

1>Setup Final DMMU Entries

1>Map Slave POST to master memory

1>I-Cache RAM Test

0>I-Cache RAM Test

1>I-Cache Tag RAM

0>I-Cache Tag RAM

1>I-Cache Valid/Predict TAGS Test

0>I-Cache Valid/Predict TAGS Test

1>I-Cache Snoop Tag Field

0>I-Cache Snoop Tag Field

1>I-Cache Branch Predict Array Test

0>I-Cache Branch Predict Array Test

1>Branch Prediction Initialization

0>Branch Prediction Initialization

1>D-Cache RAM

0>D-Cache RAM

1>D-Cache Tags

0>D-Cache Tags

1>D-Cache Micro Tags

0>D-Cache Micro Tags

1>D-Cache SnoopTags Test

0>D-Cache SnoopTags Test

1>W-Cache RAM

0>W-Cache RAM

1>W-Cache Tags

0>W-Cache Tags

1>W-Cache Valid bit Test

0>W-Cache Valid bit Test

1>W-Cache Bank valid bit Test

0>W-Cache Bank valid bit Test

1>W-Cache SnoopTAGS Test

0>W-Cache SnoopTAGS Test

1>P-Cache RAM

0>P-Cache RAM

1>P-Cache Tags

0>P-Cache Tags

1>P-Cache SnoopTags Test

0>P-Cache SnoopTags Test

1>P-Cache Status Data Test

0>P-Cache Status Data Test

1>8k DMMU TLB 0 Data

0>8k DMMU TLB 0 Data

1>8k DMMU TLB 1 Data

0>8k DMMU TLB 1 Data

1>8k DMMU TLB 0 Tags

0>8k DMMU TLB 0 Tags

1>8k DMMU TLB 1 Tags

0>8k DMMU TLB 1 Tags

1>8k IMMU TLB Data

0>8k IMMU TLB Data

1>8k IMMU TLB Tags

0>8k IMMU TLB Tags

1>FPU Registers and Data Path

0>FPU Registers and Data Path

1>FPU Move Registers

0>FPU Move Registers

1>FSR Read/Write

0>FSR Read/Write

1>FPU Block Register Test

0>FPU Block Register Test

1>FPU Branch Instructions

0>FPU Branch Instructions

1>FPU Functional Test

0>FPU Functional Test

1>Scrub Memory

0>Scrub Memory

SC Alert: SC initiating soft host system shutdown due to fault at MB.P0.T_CORE.

SC Alert: SC Request to Power Off Host.

SC Alert: TEMP_SENSOR @ MB.P0.T_CORE has exceeded high soft shutdown threshold.
1>Flush Caches

0>Flush Caches

1>L2-Cache Functional

0>L2-Cache Functional

1>L2-Cache Stress

0>L2-Cache Stress

1>IMMU Functional

0>IMMU Functional

1>DMMU Functional

0>DMMU Functional

1>I-Cache Functional

0>I-Cache Functional

1>I-Cache Parity Functional

0>I-Cache Parity Functional

1>I-Cache Parity Tag

0>I-Cache Parity Tag

SC Alert: TEMP_SENSOR @ MB.P0.T_CORE has exceeded high hard shutdown threshold.
1>I-Cache Snoop Parity Tag

0>I-Cache Snoop Parity Tag

1>D-Cache Functional

0>D-Cache Functional

1>D-Cache Parity Functional

0>D-Cache Parity Functional

1>D-Cache Parity Tag Test

0>D-Cache Parity Tag Test

1>W-Cache Functional

0>W-Cache Functional

1>Graphics Functional

1>CPU Superscalar Dispatch

0>Graphics Functional

0>CPU Superscalar Dispatch

1>SPARC Atomic Instruction Test

0>SPARC Atomic Instruction Test

1>Non SPARC Atomic Instruction Test

0>Non SPARC Atomic Instruction Test

1>SOFTINT Register and Interrupt Test

1>Branch Memory Test

0>SOFTINT Register and Interrupt Test

0>Branch Memory Test

1>Fast ECC test

0>Fast ECC test

1>System ECC test

0>System ECC test

0>XBus SRAM

0>IO-Bridge SouthBridge Remap Devs      

0>JBUS quick check

0>  to IO-bridge_0

0>  to IO-bridge_1

0>IO-Bridge unit 0 sram      test  

0>IO-Bridge unit 0 reg       test  

0>IO-Bridge unit 0 mem       test  

0>IO-Bridge unit 0 PCI id    test  

0>IO-Bridge unit 0 interrupt test  

0>IO-Bridge unit 1 sram      test  

0>IO-Bridge unit 1 reg       test  

0>IO-Bridge unit 1 mem       test  

0>IO-Bridge unit 1 PCI id    test  

0>IO-Bridge unit 1 interrupt test  

0>IO-Bridge unit 0 init      test  

1>IO-Bridge unit 0 sram      test  

1>IO-Bridge unit 0 reg       test  

1>IO-Bridge unit 0 mem       test  

1>IO-Bridge unit 0 PCI id    test  

1>IO-Bridge unit 0 interrupt test  

1>IO-Bridge unit 1 init      test  

1>IO-Bridge unit 1 sram      test  

1>IO-Bridge unit 1 reg       test  

1>IO-Bridge unit 1 mem       test  

1>IO-Bridge unit 1 PCI id    test  

1>IO-Bridge unit 1 interrupt test  

1>Print Mem Config

1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.

1>Memory interleave set to 0

1> Bank 0 1024MB : 00000010.00000000 -> 00000010.40000000.

1> Bank 1 1024MB : 00000011.00000000 -> 00000011.40000000.

0>Print Mem Config

0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.

0>Memory interleave set to 0

0> Bank 0 1024MB : 00000000.00000000 -> 00000000.40000000.

0> Bank 1 1024MB : 00000001.00000000 -> 00000001.40000000.

1>Block Memory

0>Block Memory

1>Test 1069547520 bytes on bank 0....

0>Test 1063256064 bytes on bank 0....

0>0% Done...

0>1% Done...

0>3% Done...

0>4% Done...

0>6% Done...

0>7% Done...

0>9% Done...

0>10% Done...

0>11% Done...

0>13% Done...

0>14% Done...

0>16% Done...

0>17% Done...

0>18% Done...

0>20% Done...

0>21% Done...

0>23% Done...

0>24% Done...

0>25% Done...

SC Alert: Host system has shut down.

v240关机,原因是cpu的跳线主频不一致导致的,高工把我们坏的主板上那下两个跳线帽安装到新主板一排的第一和第二的位置使得cpu的跳线主频是1280MHZ,问题解决。

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